In a typical computer system, data may be exchanged between a memory device and one or more peripheral devices under the control of a host processor. Since memory devices generally communicate data through parallel driven data buses and peripheral devices generally communicate data through serial driven communication channels, one or more interface circuits providing parallel-to-serial and/or serial-to-parallel data conversion are required in such computer systems.
U.S. Pat. No. 3,975,712 and U.S. Pat. No. 5,287,458, which are both incorporated herein by this reference, describe such computer systems and in particular, communication interface circuits employing shift registers for performing such parallel-to-serial and serial-to-parallel conversion functions.
It is a primary object of the present invention, however, to provide a simpler and more cost effective circuit for performing such parallel-to-serial and serial-to-parallel conversion functions in a communication interface unit facilitating data transfers between a parallel drive data bus and one or more serial driven communication channels in a computer system.